Home › Categories › computer-science › Microprocessors Tutorial: Learn 8086 from Scratc…
computer-science4 min read

Microprocessors Tutorial: Learn 8086 from Scratch (2026)

Sandip Mhaske • Ayodhyya • computer-science

Microprocessors Tutorial: Learn 8086 from Scratch (2026)

Published:  |  Category: Computer Science  |  Reading time: ~15 min
Microprocessors Tutorial: Learn 8086 from Scratch (2026)

The 8086 microprocessor, introduced by Intel in 1978, launched the x86 architecture that still powers most desktop and server computers today. Studying the 8086 is like learning the roots of a family tree — its segmented memory model, register set, and instruction architecture directly influenced every x86 processor since. This tutorial provides a hands-on introduction to the 8086 architecture, assembly programming, memory addressing, and interrupt handling.

We will write assembly programs that manipulate registers, access memory, handle interrupts, and interface with peripherals.

📖 Table of Contents
  1. 8086 Architecture and Register Set
  2. Memory Addressing Modes
  3. 8086 Instruction Set and Programming
  4. Interrupts and Interrupt Vector Table
  5. Memory Segmentation and Addressing
  6. Interfacing with Peripherals: 8255 PPI

8086 Architecture and Register Set

The 8086 has fourteen 16-bit registers. General-purpose: AX (accumulator), BX (base), CX (count), DX (data). Each accessible as two 8-bit halves. Pointer/index: SP, BP, SI, DI. Segment: CS, DS, SS, ES. The flag register contains status bits: Carry, Parity, Zero, Sign, Overflow, Interrupt enable, and Trap.

ORG 100h
MOV AX, 1234h; MOV BX, 5678h; MOV CX, 0ABCDh; MOV DX, 0FFFFh
ADD AX, BX; SUB CX, DX
MOV AL, 55h; MOV BH, 0AAh
PUSH AX; PUSH BX; POP CX; POP DX
MOV AH, 4Ch; INT 21h
END

Memory Addressing Modes

The 8086 supports multiple addressing modes: Register, Immediate, Direct, Register Indirect, Based, Indexed, and Based Indexed. Effective address = Base + Index + Displacement. Physical address = segment*16 + offset. The default data segment is DS; BP uses SS by default.

ORG 100h
MOV AX, 0700h; MOV DS, AX
MOV WORD [100h], 0ABCDh; MOV WORD [102h], 1234h
MOV AX, [100h]
MOV BX, 100h; MOV DX, [BX]
MOV SI, 2; MOV CX, [BX+SI]
MOV AX, [BX+SI+4]
MOV SI, 100h; MOV DI, 200h; MOV CX, 4; REP MOVSB
RET
END

8086 Instruction Set and Programming

The 8086 instruction set includes data transfer (MOV, XCHG, LEA), arithmetic (ADD, SUB, MUL, DIV), logical (AND, OR, XOR, NOT, SHL, SHR), string operations (MOVS, CMPS, SCAS, LODS, STOS), control flow (JMP, conditional jumps, LOOP, CALL, RET). Conditional jumps check flag states: JZ/JE, JNZ, JC, JNC, JO, JS.

ORG 100h
MOV CX, 8
MOV [200h],5; MOV [201h],2; MOV [202h],8; MOV [203h],1
MOV [204h],9; MOV [205h],3; MOV [206h],7; MOV [207h],4
DEC CX
outer: MOV DI, CX; MOV SI, 0
inner: MOV AL, [200h+SI]
CMP AL, [200h+SI+1]; JBE no_swap
XCHG AL, [200h+SI+1]; MOV [200h+SI], AL
no_swap: INC SI; DEC DI; JNZ inner
loop outer
RET
END

Interrupts and Interrupt Vector Table

The 8086 supports hardware interrupts (INTR, NMI) and software interrupts (INT). The IVT occupies addresses 00000h-003FFh with 256 entries of 4 bytes each (segment:offset). INT 21h provides DOS services, INT 10h video, INT 16h keyboard. The Interrupt flag (IF) enables maskable hardware interrupts.

ORG 100h
MOV AX,0; MOV ES,AX; MOV BX,60h*4
MOV AX,ES:[BX]; MOV old_ofs,AX
MOV AX,ES:[BX+2]; MOV old_seg,AX
CLI; MOV WORD ES:[BX],OFFSET handler; MOV ES:[BX+2],CS; STI
INT 60h
CLI; MOV AX,old_ofs; MOV ES:[BX],AX; MOV AX,old_seg; MOV ES:[BX+2],AX; STI
RET
handler: PUSH AX; PUSH DX; MOV AH,09h; MOV DX,OFFSET msg; INT 21h; POP DX; POP AX; IRET
msg DB 'Handler!$'
old_ofs DW 0; old_seg DW 0
END

Memory Segmentation and Addressing

The 8086 uses a segmented memory model with a 20-bit address bus, accessing 1 MB. Physical = (segment<<4) + offset. Segments are 64 KB and can overlap. Near pointers are 16-bit offsets; far pointers include both segment and offset (32 bits). The A20 gate issue plagued compatibility for years.

ORG 100h
MOV WORD [300h], 0100h; MOV WORD [302h], 0800h
JMP FAR [300h]
MOV AX, 0B800h; MOV ES, AX; MOV ES:[0], 41h; MOV ES:[1], 07h
MOV AX, CS; MOV BX, DS; MOV CX, SS; MOV DX, ES
RET
END

Interfacing with Peripherals: 8255 PPI

The 8255 PPI provides three 8-bit I/O ports (A, B, C) configurable in different modes. Mode 0 gives basic I/O. The control register at base+3 sets mode and port directions. The 8255 was used in the original IBM PC for keyboard, speaker, and DIP switch interfaces.

PORTA EQU 60h; PORTB EQU 62h; PORTC EQU 64h; CTRL EQU 66h
MOV AL, 80h; OUT CTRL, AL    ; Mode 0, all output
MOV AL, 0FFh; OUT PORTA, AL
MOV AL, 55h; OUT PORTB, AL
IN AL, PORTA
MOV AL, 10001001b; OUT CTRL, AL
IN AL, PORTC; AND AL, 0Fh
SEG_TABLE DB 3Fh,06h,5Bh,4Fh,66h,6Dh,7Dh,07h
          DB 7Fh,6Fh,77h,7Ch,39h,5Eh,79h,71h
MOV BX, OFFSET SEG_TABLE; XLAT; OUT PORTA, AL
RET
END

Frequently Asked Questions

Why does the 8086 have a segmented memory model?

Segmentation allowed the 8086 to address 1 MB with 16-bit registers (20-bit address = segment*16 + offset) and provided memory protection by separating code, data, and stack segments.

What is the difference between NEAR and FAR pointers?

A NEAR pointer is a 16-bit offset within the current segment. A FAR pointer includes both segment (16-bit) and offset, accessing the full 1 MB but requiring two memory words.

How do hardware interrupts work on the 8086?

External devices trigger the INTR pin. The CPU completes the current instruction, pushes flags and return address, looks up the handler from the IVT (interrupt*4), and jumps to the handler.

What was the A20 gate issue?

The 80286 had 24 address lines (16 MB). For 8086 compatibility, the A20 line was gated. When disabled, addresses above 1 MB wrapped around, causing compatibility problems.

Originally published on Ayodhyyya. Last updated June 1, 2026.